Semiconductor devices typically contain several levels of metal interconnect to connect various elements, such as transistors, capacitors and resistors, to each other. A level of metal interconnect is connected to other levels of metal interconnect through conductive vias. Traditionally, the metal interconnects comprised an aluminum alloy along with barrier layers and the conductive vias comprised tungsten.
However, copper interconnects are replacing the traditional aluminum interconnects. Copper interconnects are being formed using dual damascene processes in which the dielectrics are formed first. A trench is etched in an intrametal dielectric (IMD) for the interconnect lines. A via may be etched in an underlying interlevel dielectric (ILD). The trench and any vias are then both filled with copper using the same process. A barrier layer is deposited followed by a copper seed layer. Electrochemical deposition (ECD) is then used to fill the trench and vias with copper. The ECD process overfills the trench and the excess copper is removed by CMP.
It is sometimes desirable to remove a copper interconnect level without damaging the underlying structure (e.g., the IMD, ILD, vias, contacts). This is typically desired during failure analysis (FA) of a semiconductor device.
Traditional wet etching techniques can not be applied to selectively delayer copper interconnect levels. In older technologies using aluminum interconnects, the vias are typically tungsten plugs which are available to act as an etch stop. (Although, if the tungsten plugs did not hold up the underlying Al would be etched perhaps loosing the defect.) However, in copper interconnects, the conductive vias comprise the same materials as the interconnect lines (i.e., copper and barrier layers) and therefore cannot serve as an etch stop.
Currently, the only available tools for selective delayering of copper interconnects are parallel polishing and plasma etching. These processes are painstaking and very time consuming. Lapping is a manual process normally. There is no real way to understand how much material has been lapped so the analyst must constantly inspect the sample. The layers are now so thin that the inspection must be performed on an SEM. Loading, inspection and unloading is time consuming. The SEM is a costly tool. Automated lapping procedures are currently difficult to setup. They suffer from the same problem as manual lapping when it comes to inspection of the layers being removed. In addition, there is no etch stop for lapping. Plasma etching does have some laser end point detection but for processed die the endpoint detection is subject to interpretation. An analyst must still inspect the device to see if the correct surface has been removed to the proper depth.